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19-5122; Rev 1; 4/10
TION KIT EVALUA BLE VAILA A
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Features
S Dual, 256-Tap Linear Taper Positions S Single +1.7V to +5.5V Supply Operation S Low 12A Quiescent Supply Current S 10kI, 50kI, 100kI End-to-End Resistance Values S I2C-Compatible Interface S Wiper Set to Midscale on Power-Up S -40NC to +125NC Operating Temperature Range
General Description
The MAX5392 dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer offers three end-to-end resistance values of 10kI, 50kI, and 100kI. Operating from a single +1.7V to +5.5V power supply, the device provides a low 35ppm/NC end-to-end temperature coefficient. The device features an I2C interface. The small package size, low supply operating voltage, low supply current, and automotive temperature range of the MAX5392 makes the device uniquely suited for the portable consumer market, battery-backup industrial applications, and the automotive market. The MAX5392 is specified over the automotive -40NC to +125NC temperature range and is available in a 16-pin TSSOP package.
MAX5392
Ordering Information
PART MAX5392LAUE+ PIN-PACKAGE 16 TSSOP 16 TSSOP 16 TSSOP END-TO-END RESISTANCE (kI) 10 50 100
Applications
Low-Voltage Battery Applications Portable Electronics Mechanical Potentiometer Replacement Offset and Gain Control Adjustable Voltage References/Linear Regulators Automotive Electronics
MAX5392MAUE+ MAX5392NAUE+
Note: All devices are specified over the -40C to +125NC operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
VDD CHARGE PUMP SCL SDA A0 A1 A2 LATCH I2C POR BYP HA WA LA
LATCH
256 DECODER HB
MAX5392
256 DECODER WB LB GND
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6V H_, W_, L_ to GND ......................................-0.3V to the lower of (VDD + 0.3V) and +6V All Other Pins to GND .............................................-0.3V to +6V Continuous Current in to H_, W_, and L_ MAX5392L ..................................................................... Q5mA MAX5392M .................................................................... Q2mA MAX5392N..................................................................... Q1mA Continuous Power Dissipation (TA = +70NC) 16-Pin TSSOP (derate 11.1mW/NC above +70NC) ...888.9mW Operating Temperature Range ....................... -40NC to +125NC Junction Temperature ....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity Dual Code Matching Ratiometric Resistor Tempco Full-Scale Error SYMBOL N INL DNL (Note 2) (Note 2) Register A = Register B (DVW/VW)/DT, no load MAX5392L Code = FFh MAX5392M MAX5392N MAX5392L Zero-Scale Error DC PERFORMANCE (Variable Resistor Mode) Integral Nonlinearity Differential Nonlinearity Wiper Resistance Terminal Capacitance Wiper Capacitance End-to-End Resistor Tempco End-to-End Resistor Tolerance R-INL R-DNL RWL CH_, CL_ CW_ TCR DRHL MAX5392L (Note 3) MAX5392M (Note 3) MAX5392N (Note 3) (Note 3) (Note 4) Measured to GND Measured to GND No load Wiper not connected -25 10 50 35 +25 -1.5 -0.75 -0.5 -0.5 +1.5 +0.75 +0.5 +0.5 200 LSB LSB I pF pF ppm/NC % Code = 00h MAX5392M MAX5392N -3 -1 -0.5 CONDITIONS MIN 256 -0.5 -0.5 -0.5 5 -2.2 -0.6 -0.3 2.2 0.6 0.3 3 1.0 0.5 LSB LSB +0.5 +0.5 +0.5 TYP MAX UNITS Tap LSB LSB LSB ppm/NC
DC PERFORMANCE (Voltage Divider Mode)
DC PERFORMANCE (Resistor Characteristics)
2
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Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER AC PERFORMANCE Crosstalk -3dB Bandwidth Total Harmonic Distortion Plus Noise Wiper Settling Time Charge-Pump Feedthrough at W_ POWER SUPPLIES Supply Voltage Range Standby Current DIGITAL INPUTS Minimum Input High Voltage Maximum Input Low Voltage Input Leakage Current Input Capacitance TIMING CHARACTERISTICS--I2C (Notes 7 and 8) Maximum SCL Frequency Setup Time for START Condition Hold Time for START Condition SCL High Time SCL Low Time fSCL tSU:STA tHD:STA tHIGH tLOW 0.6 0.6 0.6 1.3 400 kHz Fs Fs Fs Fs VIH VIL VDD = 2.6V to 5.5V VDD = 1.7V to 2.6V VDD = 2.6V to 5.5V VDD = 1.7V to 2.6V -1 5 70 75 30 25 +1 % x VDD % x VDD FA pF VDD VDD = 5.5V VDD = 1.7V 1.7 27 12 5.5 V FA BW (Note 5) Code = 80H, 10pF load, VDD = 1.8V MAX5392L MAX5392M MAX5392N -90 600 100 50 0.02 400 1200 2200 600 nVP-P ns % kHz dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5392
THD+N
Measured at W, VH_ = 1VRMS at 1kHz MAX5392L (Note 6) MAX5392M MAX5392N
tS VRW
fCLK = 600kHz, CBYP = 0nF
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3
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER Data Setup Time Data Hold Time SDA, SCL Rise Time SDA, SCL Fall Setup Time for STOP Condition Bus Free Time Between STOP and START Condition Pulse Suppressed Spike Width Capacitive Load for Each Bus SYMBOL tSU:DAT tHD:DAT tR tF tSU:STO tBUF tSP CB (Note 9) Minimum power-up rate = 0.2V/Fs 0.6 1.3 50 400 CONDITIONS MIN 100 0 0.3 0.3 TYP MAX UNITS ns Fs Fs Fs Fs Fs ns pF
Note 1: All devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design and characterization. Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter. Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and 40FA for the 100kI configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150FA for the 10kI configuration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration. Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 to W_ with L_ = GND. RW_ = (VW_ - VH_)/IW_. Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure WB. Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND, and the wiper terminal is loaded with 10pF capacitance to ground. Note 7: Digital timing is guaranteed by design and characterization, not production tested. Note 8: The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and timed from a voltage level of (VIL + VIH)/2. Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. For I2C-bus specification information from NXP Semiconductor (formerly Philips Semiconductor), refer to the UM10204: I2C-Bus Specification and User Manual.
H
N.C.
W
W
L
L
Figure 1. Voltage-Divider and Variable Resistor Configurations
4
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Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Typical Operating Characteristics
(VDD = 1.8V, TA = +25C, unless otherwise noted.)
MAX5392
SUPPLY CURRENT vs. TEMPERATURE
MAX5392 toc01
SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
MAX5392 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
30
MAX5392 toc03
30 25 SUPPLY CURRENT (A) 20 15 10 VDD = 1.8V 5 0 VDD = 5V VDD = 2.6V
10,000
SUPPLY CURRENT (A)
1000
VDD = 5V IDD (A)
25
100
VDD = 2.6V
20
10 VDD = 1.8V 1
15
10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DIGITAL INPUT VOLTAGE (V) 1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 VDD (V)
-40 -20 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
RESISTANCE (W_-TO-L_) vs. TAP POSITION (10kI)
MAX5392 toc04
RESISTANCE (W_-TO-L_) vs. TAP POSITION (50kI)
MAX5392 toc05
RESISTANCE (W_-TO-L_) vs. TAP POSITION (100kI)
90 W_-TO-L_ RESISTANCE (kI) 80 70 60 50 40 30 20 10 0
MAX5392 toc06
10 9
W_-TO-L_ RESISTANCE (kI)
50 45
W_-TO-L_ RESISTANCE (kI)
100
8 7 6 5 4 3 2 1 0 0 51 102 153 204
40 35 30 25 20 15 10 5 0
255
0
51
102
153
204
255
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP POSITION
WIPER RESISTANCE vs. WIPER VOLTAGE (10kI)
MAX5392 toc07
END-TO-END RESISTANCE PERCENTAGE CHANGE vs. TEMPERATURE
MAX5392 toc08
VARIABLE RESISTOR DNL vs. TAP POSITION (10kI)
0.08 0.06 0.04 DNL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 IWIPER = 150A 0 51 102 153 204 255
MAX5392 toc09
0.05 END-TO-END RESISTANCE % CHANGE 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 50kI 10kI 100kI
0.10
140
WIPER RESISTANCE (I)
120
100
VDD = 5V
80
VDD = 1.8V VDD = 2.6V
60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 WIPER VOLTAGE (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
TAP POSITION
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5
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25C, unless otherwise noted.)
VARIABLE RESISTOR DNL vs. TAP POSITION (50kI)
MAX5392 toc10
VARIABLE RESISTOR DNL vs. TAP POSITION (100kI)
MAX5392 toc11
VARIABLE RESISTOR INL vs. TAP POSITION (10kI)
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX5392 toc12
0.10 0.08 0.06 0.04 DNL (LSB) 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 51 102 153 204 IWIPER = 30A 0.02
0.10 0.08 0.06 0.04 DNL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 IWIPER = 15A 0 51 102 153 204
1.0
IWIPER = 150A 0 51 102 153 204 255
255
255
TAP POSITION
TAP POSITION
TAP POSITION
VARIABLE RESISTOR INL vs. TAP POSITION (50kI)
MAX5392 toc13
VARIABLE RESISTOR INL vs. TAP POSITION (100kI)
MAX5392 toc14
VOLTAGE-DIVIDER DNL vs. TAP POSITION (10kI)
0.08 0.06 0.04 DNL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10
MAX5392 toc15
0.5 0.4 0.3 0.2 INL (LSB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 51 102 153 204 IWIPER = 30A 0.1
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 IWIPER = 15A 0 51 102 153 204
0.10
255
255
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP POSITION
VOLTAGE-DIVIDER DNL vs. TAP POSITION (50kI)
MAX5392 toc16
VOLTAGE-DIVIDER DNL vs. TAP POSITION (100kI)
MAX5392 toc17
VOLTAGE-DIVIDER INL vs. TAP POSITION (10kI)
0.4 0.3 0.2
INL (LSB)
MAX5392 toc18
0.10 0.08 0.06 0.04 DNL (LSB) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 51 102 153 204
0.10 0.08 0.06 0.04
DNL (LSB)
0.5
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
255
0
51
102
153
204
255
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP POSITION
6
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Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25C, unless otherwise noted.)
MAX5392
VOLTAGE-DIVIDER INL vs. TAP POSITION (50kI)
MAX5392 toc19
VOLTAGE-DIVIDER INL vs. TAP POSITION (100kI)
0.4 0.3 0.2
INL (LSB)
MAX5392 toc20
0.5 0.4 0.3 0.2
INL (LSB)
0.5
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 51 102 153 204 255 TAP POSITION
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 51 102 153 204 255 TAP POSITION
TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 10kI
VDD = 5V
MAX5392 toc21
TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 50kI
VDD = 5V VW_-L_ 20mV/div
MAX5392 toc22
VW_-L_ 20mV/div
SCL 5V/div
SCL 5V/div
400ns/div
1s/div
TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 100kI
VDD = 5V
P0WER-ON TRANSIENT (50kI)
MAX5392 toc24
MAX5392 toc23
VW_-L_ 20mV/div
VW_-L_ 1V/div
SCL 5V/div
VCC 5V/div
1s/div
2s/div
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7
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25C, unless otherwise noted.)
MIDSCALE FREQUENCY RESPONSE (10kI)
MAX5392 toc25
MIDSCALE FREQUENCY RESPONSE (50kI)
MAX5392 toc26
MIDSCALE FREQUENCY RESPONSE (100kI)
MAX5392 toc27
10 VDD = 5V 0 GAIN (dB)
10
10
0 GAIN (dB)
VDD = 5V
0 GAIN (dB)
VDD = 5V
-10 VDD = 1.8V -20 VIN = 1VP-P CW = 10pF -30 0.01 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
-10
VDD = 1.8V
-10 VDD = 1.8V -20
-20 VIN = 1VP-P CW = 10pF -30 0.01 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
VIN = 1VP-P CW = 10pF -30 0.01 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
CROSSTALK vs. FREQUENCY
MAX5392 toc28
-20 CROSSTALK (dB) -40 -60 -80 -100 -120 10kI -140 0.01 0.1 1 10 100 100kI 50kI
0.18 0.16 0.14 THD+N (%) 0.12 0.10 0.08 0.06 0.04 0.02 0 0.01 0.1 1 FREQUENCY (kHz) 10 50kI 100kI 10kI
MAX5392 toc29
0.20
100 RAMP TIME (ms) 80 60 40 20 0
1000
FREQUENCY (kHz)
100
0
0.02
0.04
0.05
0.08
0.10
BYP CAPACITANCE (F)
CHARGE-PUMP FEEDTHROUGH AT W_ vs. CBYP
MAX5392 toc31
CHARGE-PUMP FEEDTHROUGH AT W_ vs. FREQUENCY
0.9 0.8 AMPLITUDE (VRMS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX5392 toc32
700 600 VOLTAGE (nVRMS) 500 400 300 200 100 0 0 200 400 CAPACITANCE (pF) 600
1.0
800
300
400
500
600
700
800
900
FREQUENCY (kHz)
8
______________________________________________________________________________________
MAX5392 toc30
0
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
BYP RAMP TIME vs. CBYP
120
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Pin Configuration
TOP VIEW
HA 1 WA 2 LA 3 HB 4 WB 5 LB 6 BYP 7 I.C. 8
MAX5392
+
16 VDD 15 N.C. 14 SCL 13 SDA
MAX5392
12 A0 11 A1 10 A2 9 GND
TSSOP
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME HA WA LA HB WB LB BYP I.C. GND A2 A1 A0 SDA SCL N.C. VDD FUNCTION Resistor A High Terminal. The voltage at HA can be higher or lower than the voltage at LA. Current can flow into or out of HA. Resistor A Wiper Terminal Resistor A Low Terminal. The voltage at LA can be higher or lower than the voltage at HA. Current can flow into or out of LA. Resistor B High Terminal. The voltage at HB can be higher or lower than the voltage at LB. Current can flow into or out of HB. Resistor B Wiper Terminal Resistor B Low Terminal. The voltage at LB can be higher or lower than the voltage at HB. Current can flow into or out of LB. Internal Power-Supply Bypass. For additional charge-pump filtering, bypass to GND with a capacitor close to the device. Internally Connected. Connect to GND. Ground Address Input 2. Connect to VDD or GND. Address Input 1. Connect to VDD or GND. Address Input 0. Connect to VDD or GND. I2C-Compatible Serial-Data Input/Output. A pullup resistor is required. I2C-Compatible Serial-Clock Input. A pullup resistor is required. No Connection. Not internally connected. Power-Supply Input. Bypass VDD to GND with a 0.1FF capacitor close to the device.
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9
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
Detailed Description
The MAX5392 dual, 256-tap, volatile, low-voltage linear taper digital potentiometer offers three end-to-end resistance values of 10kI, 50kI, and 100kI. The potentiometer consists of 255 fixed resistors in series between terminals H_ and L_. The potentiometer wiper, W_, is programmable to access any one of the 256 tap points on the resistor string. The potentiometers are programmable independently of each other. The MAX5392 features an I2C interface. TThe MAX5392 contains an internal charge pump that guarantees the maximum wiper resistance, RWL, to be less than 200 for supply voltages down to 1.7V. Pins H_, W_, and L_ are still required to be less than VDD + 0.3V. A bypass input, BYP, is provided to allow additional filtering of the charge-pump output, further reducing clock feedthrough that can occur on H_, W_, or L_. The nominal clock rate of the charge pump is 600kHz. BYP should remain resistively unloaded as any additional load would increase clock feedthrough. See the Charge-Pump Feedthrough at W_ vs. CBYP graph in the Typical Operating Characteristics for CBYP sizing guidelines with respect to clock feedthrough to the wiper. The value of CBYP does affect the startup time of the charge pump; however, CBYP does not impact the ability to communicate with the device, nor is there a minimum CBYP requirement. The maximum wiper impedance specification is not guaranteed until the charge pump is fully settled. See the BYP Ramp Time vs. CBYP graph in the Typical Operating Characteristics for CBYP impact on charge-pump settling time. The interface contains a shift register that decodes the command and address bytes, routing the data to the appropriate control registers. Data written to a control register immediately updates the wiper position. The wipers A and B power up in midposition, D[7:0] = 80h. Serial Addressing The MAX5392 operates as a slave device that receives data through an I2C/SMBusK-compatible 2-wire serial interface. The interface uses a serial-data access line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to the port and generates the SCL clock that synchronizes the data transfer. See Figure 2. Connect a pullup resistor, typically 4.7kI, between each of the SDA and SCL lines to a voltage between VDD and 5.5V. I2C
I2C Digital Interface
Charge Pump
tHD:STA SDA tSU:DAT tLOW SCL tHD:STA tR START CONDITION (S) tHIGH tF REPEATD START CONDITION (Sr) ACKNOWLEDGE (A) tHD:DAT tSU:DTA
tSU:STD
tBUF
STOP CONDITION START CONDITION (P) (S)
Figure 2. I2C Serial-Interface Timing Diagram
SMBus is a trademark of Intel Corp. 10 _____________________________________________________________________________________
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Each transmission consists of a START (S) condition sent by a master, followed by a 7-bit slave address plus a NOP/W bit. See Figures 3, 4, and 7. START and STOP Conditions SCL and SDA remain high when the interface is inactive. A master controller signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. The master controller issues a STOP condition by transitioning the SDA from low to high while SCL is high, after finishing communicating with the slave. The bus is then free for another transmission. See Figure 2. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high. See Figure 5. Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data. See Figure 6. Each byte transferred requires a total of 9 bits. The master controller generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line remains stable low during the high period of the clock pulse.
MAX5392
SDA
SCL S START CONDITION P
STOP CONDITION
Figure 3. START and STOP Conditions
SDA
0
1
0
1
A2
A1
A0
NOP/W
ACK
START SCL
MSB
LSB
Figure 4. Slave Address
SDA
CHANGE OF DATA ALLOWED
SCL
DATA STABLE, DATA VALID
Figure 5. Bit Transfer ______________________________________________________________________________________ 11
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 NOT ACKNOWLEDGE SDA 9
ACKNOWLEDGE
Figure 6. Acknowledge
ACKNOWLEDGE HOW CONTROL BYTE AND DATA BYTE MAP INTO DEVICE REGISTERS ACKNOWLEDGE S 0 A A A P D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS NOP/W
COMMAND BYTE
1 DATA BYTE
Figure 7. Command and Single Data Byte Received
Slave Address The MAX5392 includes a 7-bit slave address (Figure 4). The 8th bit following the 7th bit of the slave address is the NOP/W bit. Set the NOP/W bit low for a write command and high for a no-operation command. The device does not support readback. The device provides three address inputs (A0, A1, and A2), allowing up to eight devices to share a common bus (Table 1). The first 4 bits (MSBs) of the factory-set slave addresses are always 0101. A2, A1, and A0 set the next 3 bits of the slave address. Connect each address input to VDD or GND. Each device must have a unique address to share a common bus. Message Format for Writing Write to the devices by transmitting the device's slave address with NOP/W (8th bit) set to zero, followed by at least 2 bytes of information. The first byte of informa-
tion is the command byte. The second byte is the data byte. The data byte goes into the internal register of the device as selected by the command byte (Figure 7 and Table 2).
Table 1. Slave Addresses
ADDRESS INPUTS A2 GND GND GND GND VDD VDD VDD VDD A1 GND GND VDD VDD GND GND VDD VDD A0 GND VDD GND VDD GND VDD GND VDD SLAVE ADDRESS 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111
12
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Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer
Table 2. I2C Command Byte Summary
ADDRESS BYTE 1 SCL CYCLE NUMBER REG A REG B REG A AND B START (S) 2 3 4 5 6 7 8 9 ACK (A) 10 11 12 COMMAND BYTE 13 14 15 16 17 18 ACK (A) 19 20 21 DATA BYTE 22 23 24 25 26 27 ACK (A) STOP (P)
MAX5392
A6
A5
A4
A3
A2
A1
A0
W
R7
R6
R5
R4
R3
R2
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0
1 1 1
0 0 0
1 1 1
A2 A2 A2
A1 A1 A1
A0 A0 A0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
0 1 1
1 0 1
D7 D7 D7
D6 D6 D6
D5 D5 D5
D4 D4 D4
D3 D3 D3
D2 D2 D2
D1 D1 D1
D0 D0 D0
Command Byte Use the command byte to select the destination of the wiper data. See Table 2. Command Descriptions REG A: The data byte writes to register A and the wiper of potentiometer A moves to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wiper to the position closest to LA. D[7:0] = FFh moves the wiper closest to HA. D[7:0] is 80h following power-on. REG B: The data byte writes to register B and the wiper of potentiometer B moves to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wiper to the position closest to LB. D[7:0] = FFh moves the wiper to the position closest to HB. D[7:0] is 80h following power-on. REG A and B: The data byte writes to registers A and B and the wipers of potentiometers A and B move to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wipers to the position closest to L_. D[7:0] = FFh moves the wipers to the position closest to H_. D[7:0] is 80h following power-on.
Applications Information
Figure 8 shows a potentiometer adjusting the gain of a noninverting amplifier. Figure 9 shows a potentiometer adjusting the gain of an inverting amplifier. Figure 10 shows an adjustable dual linear regulator using a dual potentiometer as two variable resistors.
H W VIN VOUT L
Variable Gain Amplifier
Adjustable Dual Regulator
Figure 9. Variable Gain Inverting Amplifier
VOUT1 VOUT2
OUT1 OUT2 VIN VOUT V+ IN
MAX8866
W SET1
H
H
W L L
W L H
SET2
Figure 8. Variable Gain Noninverting Amplifier Figure 10. Adjustable Dual Linear Regulator ______________________________________________________________________________________ 13
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
Figure 11 shows an adjustable voltage reference circuit using a potentiometer as a voltage-divider.
Adjustable Voltage Reference
Figure 15 shows a programmable filter using a dual potentiometer.
Programmable Filter
Figure 12 shows a variable gain current to voltage converter using a potentiometer as a variable resistor. Figure 13 shows a positive LCD bias control circuit using a potentiometer as a voltage-divider. Figure 14 shows a positive LCD bias control circuit using a potentiometer as a variable resistor.
Variable Gain Current to Voltage Converter
Figure 16 shows an offset voltage adjustment circuit using a dual potentiometer.
Offset Voltage Adjustment Circuit
LCD Bias Control
PROCESS: BiCMOS
Chip Information
+2.5V IN OUT H W VREF
1.8V H W
VOUT
MAX6037
L GND L
Figure 11. Adjustable Voltage Reference
Figure 13. Positive LCD Bias Control Using a Voltage Divider
1.8V R3 H W
IS
R1 L
R2
H W
VOUT
VOUT
L
VOUT = IS x ((R3 x (1 + R2/R1)) + R2)
Figure 12. Variable Gain I-to-V Converter
Figure 14. Positive LCD Bias Control Using a Variable Resistor
14
_____________________________________________________________________________________
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
1.8V WB
VIN
WA LB HA
VOUT VOUT
LA
HB R3
R1 HA R2 LA HB
WA
WB LB
Figure 15. Programmable Filter
Figure 16. Offset Voltage Adjustment Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 16 TSSOP PACKAGE CODE U16+2 DOCUMENT NO. 21-0066
______________________________________________________________________________________
15
Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer MAX5392
Revision History
REVISION NUMBER 0 1 REVISION DATE 1/10 4/10 Initial release Added Soldering Temperature in Absolute Maximum Ratings; corrected code in Conditions of -3dB Bandwidth specification in Electrical Characteristics DESCRIPTION PAGES CHANGED -- 2, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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